1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method for the same. In particular, the invention relates to a semiconductor device having a trench gate, and a manufacturing method for the same.
2. Description of Related Art
Up to now, a vertical power MOSFET (Metal-Oxide Semiconductor Field Effect Transistor) has been known as a high-voltage MOSFET. In a trench-gate type MOSFET typifying such a power MOSFET, a gate electrode is provided inside a trench, and a channel region is formed in a vertical direction to easily shrink a cell pitch and realize a high degree of integration and a low on-resistance. However, a trench type MOSFET has a large gate capacitance (parasitic capacitance of a gate bottom portion), which leads to a great obstacle to the application to a high-speed switching element. Further, when a large amount of current (overcurrent) flows through the MOSFET, charges are concentrated around corners of the trench bottom, and a gate oxide film easily breaks. Accordingly, there is an increasing demand to reduce a gate capacitance and provide the gate oxide film from breaking due to the charge concentration.
As conventional trench-gate type MOSFETs, for example, a semiconductor device disclosed in Japanese Unexamined Patent Application Publication No. 2004-31963 has been known. In the MOSFET disclosed in Japanese Unexamined Patent Application Publication No. 2004-31963, a gate oxide film is formed with a large thickness at the trench bottom to reduce a gate capacitance.
FIGS. 8A to 8C show a manufacturing method for the conventional semiconductor device disclosed in Japanese Unexamined Patent Application Publication No. 2004-31963. In particular, FIGS. 8A to 8C show a method of forming a gate oxide film inside the trench. First, an epitaxial layer 213 is formed on a silicon substrate 211, and formation of a trench 203a proceeds from the front surface side of the epitaxial layer 213. As shown in FIG. 8A, a mask 801 is formed so as to expose an opening of the trench 203a, and impurities such as As (arsenic) are injected to the bottom of the trench 203a. As shown in FIG. 8B, a high-concentration region 802 is then formed below the trench 203a As a result of heat treatment, as shown in FIG. 8C, a gate oxide film 204 is formed inside the trench 203a. At this time, an impurity concentration differs between a side portion (side surface) and a bottom portion (bottom surface) of the trench 203a, so the thickness of the gate oxide film 204 is not uniform. That is, in the high-concentration region 802 doped with impurities, oxidation proceeds at enhanced speeds to form an oxide film thicker than that of both side portions, at the bottom portion of the trench 203a (enhanced oxidation portion 803).
FIG. 9 is a sectional view of a conventional semiconductor device formed with the conventional manufacturing method of FIGS. 8A to 8C. As shown in FIG. 9, the conventional semiconductor device includes, in addition to the components of FIGS. 8A to 8C, a base diffusion layer 209 and a backgate diffusion layer 208 formed on the epitaxial layer 213, and a source diffusion layer 207 formed above the base diffusion layer 209. The base diffusion layer 209 and the source diffusion layer 207 are formed on both sides of the trench 203a, and the backgate diffusion layer 208 is formed outside the layers 207 and 209. A gate electrode 203 is formed inside the trench 203a, and an interlayer insulating film 201 is formed on the gate electrode 203. A source electrode 202 is formed on the source diffusion layer 207, the backgate diffusion layer 208, the base diffusion layer 209, and the interlayer insulating film 201, and a drain electrode 210 is formed below the silicon substrate 211.
In FIG. 9, reference numeral 901 denotes a schematic gate-drain parasitic capacitance (gate capacitance). The gate capacitance of the semiconductor device depends on a dielectric constant between the gate electrode 203 and the drain electrode 210 or a bottom area of the gate electrode 203. In the conventional semiconductor device, the gate oxide film 204 is formed with a large thickness at the bottom of the trench 203a, so a proportion of the gate oxide film 204 to a region between the gate electrode 203 and the drain electrode 210 is larger, so a dielectric constant is lowered to reduce a gate capacitance.
However, the conventional semiconductor device cannot solve the problem that charges are concentrated around the corners of the trench bottom when a large amount of current such as avalanche current flows.
FIG. 10 shows a current path for a large amount of current that flows through the conventional semiconductor device. In FIG. 10, denoted by 1101 are paths where the avalanche current flows. As shown in FIG. 10, in the conventional semiconductor device, when a large amount of current flows, a large amount of charges flowing from the drain electrode 210 to the bottom of the trench 203a tend to flow from the bottom portion of the trench 203a to the side surfaces thereof, so the charges are concentrated around the corners of the bottom of the trench 203a. Therefore, if a large amount of current flows, the gate oxide film would break due to the charge concentration.
Further, in the conventional semiconductor device, when the gate oxide film is formed using the method of FIGS. 8A to 8C, a gate oxide film cannot be formed with sufficient thickness depending on conditions such as manufacturing parameters, and a high-concentration layer remains in some cases.
FIG. 11 shows an example where the enhanced oxidation portion 803 is not sufficiently oxidized, and the high-concentration layer 802 remains in the epitaxial layer 213. In this case, the high-concentration layer 802 remains near the bottom of the trench 203a, and an impurity concentration in this portion is changed. That is, an impurity concentration around the high-concentration layer 802 is higher than the rest of the epitaxial layer 213. As shown in FIG. 11, when a normal drain-source current Ids flows, the current Ids flows around the high-concentration layer 802. Therefore, if the high-concentration layer is not completely oxidized and remains, an operational characteristic (operating voltage or on-resistance) of the semiconductor device (transistor) is affected.
In particular, as shown in FIGS. 8A to 8C, according to the conventional manufacturing method, the thin oxide film at the side portions of the trench and the thick oxide film at the trench bottom are formed through the same step. Hence, it is very difficult to form only the gate oxide film at the trench bottom with a large thickness. For example, in order to further accelerate enhanced oxidation for increasing the thickness of the oxide film at the trench bottom, dosage of an impurity needs to be increased. In this case, as shown in FIG. 11, there is a high possibility that the high-concentration layer remains.
As mentioned above, in the conventional semiconductor device, even though the thickness of the oxide film at the trench bottom increases to reduce a gate capacitance, when a large amount of current such as avalanche current flows, charges are concentrated around the corners of the trench bottom, so the gate oxide film is broken in some cases.